1. Technical Field of the Invention
The present invention relates to a method and circuitry for performing non-arithmetic operations. In particular, but not exclusively, the invention relates to the comparison of floating point numbers.
2. Description of Related Art
Floating point units (FPU) are provided in many processor systems. Floating point units are designed to handle functions relating to floating point numbers. A floating point number is a convenient way of representing real numbers in a form which is particularly efficient for use in computer processor systems. An example is +/−1.2345×2n.
Floating point numbers may be divided into two categories: normalized; and de-normalized. Normalized numbers follow the standard format shown above and always have a leading “1”. De-normalized numbers however have a leading “0”. De-normalized numbers can be generated, for example, by dividing the smallest normalized number by 2. Some processor units will not accept or produce the de-normalized numbers. In these and other circumstances, it may be desirable to handle them in a separate manner to normalized numbers. One such method is to equate de-normalized numbers to zero. This procedure is known as “flush to zero”.
Floating point units can perform both arithmetic and non-arithmetic functions involving floating point numbers. One example of a non-arithmetic function is the comparison of two floating point numbers or operands. The floating point unit tests the two operands to see if one operand is greater than or equal to the other, returning a value indicative of the result. The test results may then be used in other operations by the floating point unit or other processors in the system.
Reference is made to FIG. 1 which shows schematically a known system for comparing two operands in a floating point unit. The operands 100 are input to a detector 110 which is arranged to detect if the operands are de-normalized. If the operands are determined to be de-normalized, part 120 flushes the de-normalized number to zero. The operands are then compared in a comparator 130. Finally, the output of the comparator is input to a result correction part 140 which makes corrections to take into account the signs of the operand.
The problem with the arrangement shown in FIG. 1 is that the various steps take place sequentially. In particular, the steps required to handle de-normalized numbers are on the critical path of the floating point unit. This means that the number of clock cycles taken in order to carry out the comparison operation including all of the steps described in relation to FIG. 1 is relatively high.
It is therefore an aim of embodiments of the present invention to address or at least mitigate the problems described previously.